FIG. 1 shows a conventional block diagram of controlling a clock phase alignment in a delay-locked loop (DLL). The DLL includes a phase-interpolated calibration unit 100, a phase detector 102, and a controller 104. The phase-interpolated calibration unit 100 is capable of receiving an input signal (not shown) and calibrates the phase of the input signal according to a reference signal in a phase domain. The phase detector 102 then detects the phase difference between a feedback signal of the phase-interpolated calibration unit 100 and the reference signal. Thereafter, the controller 104 receives the detecting results of the phase detector 102 and is necessarily required to control the phase-interpolated calibration unit 100 by an angular magnitude in the phase domain. The phase-interpolated calibration unit 100 repeatedly adjusts the phase of the feedback signal toward that of the reference signal by interpolating the phase of the feedback signal according to a control signal from the controller 104 until the phase alignment between the feedback signal and the reference signal is achieved.
However, since the phase alignment of the feedback signal to the reference signal is performed in the phase domain by interpolation, the phase-interpolated calibration unit 100 requires large power consumption. The implementation of the phase interpolation utilizes complicated current conversions for the signals when the feedback signal is interpolated to the reference signal. Particularly, while the current signal converted from the signal is quite small, additional circuits are required to solve the situation. Therefore, there is a need to additionally raise the size of the circuit so that the layout of the circuit is complicated and the cost of the clock source synchronization is increased as a result.
Moreover, in the prior art, a phase-locked loop (PLL) is usually used in the clock source synchronization; because the size of the PLL circuit is too large, thereby resulting in high-noise. In addition, the circuit layout of the PLL must be re-designed to downgrade the stability of the circuit since the manufacturing process of the PLL is changed.
Furthermore, the conventional DLL calibrates the clock phase by utilizing a plurality of phase intervals to cover a whole 360 degrees in phase domain, wherein every phase interval does not overlap with adjacent phase intervals. It causes a problem of that the controller has to change current phase interval to align the feedback signal with the reference signal when the reference signal is located just on the boundary of two adjacent phase intervals. The frequently switching between two different phase intervals, i.e. so-called heavy switching, would easily invite the mismatch between two phase intervals and noises in the DLL. The mismatch and noises could occur in the DLL due to the inherent imperfections during manufacturing process or interferences from outside of the electronic device. As a result, the frequent heavy switching will degrade the performance of the DLL.
As aforementioned, conventional DLL which calibrates the clock phase in a phase domain cannot afford the demand of different synchronization sources. The usage of PLL in synchronization source is also subjected to noise and circuit size. Further, the frequent heavy switching of conventional DLL is adverse to the performance of DLL. Consequently, there is a need to provide a novel delay-locked loop for the synchronization source to provide the electronic devices with a preferred clock phase adjustment of the feedback and the reference signal for reducing the cost and increasing operation efficiency.